LSI Logic Announces New Generation of Popular Open Standard DSP Architecture
SAN JOSE, Calif., Oct. 15 /PRNewswire/ -- LSI Logic Corporation
(NYSE: LSI) today announced the second generation of its ZSP(TM) digital
signal processor (DSP) architecture at the 2001 Microprocessor Forum in San
Jose, California.
Building on the highly successful ZSP400 superscalar DSP,
the new second generation (G2) architecture offers greatly increased
processing performance, reduced power consumption, and an enhanced feature set
and instruction set architecture (ISA), while maintaining backward
compatibility. Architectural innovations include a hardware-scheduled pipeline,
high-bandwidth memory architecture, a flexible co-processor interface,
enhancements for conditional and bit-level operations, and extended debugging
capabilities including trace and profiling features.
Exploiting the inherent
scalability of the architecture, LSI Logic plans a family of cores spanning a
range of requirements from high performance to extremely low power
consumption. ``We've had tremendous success with the original ZSP superscalar
architecture licensed by Broadcom, IBM, Conexant and others,'' said Giuseppe
Staffaroni, vice president and general manager of LSI Logic's Broadband group.
``The ZSP G2 architecture extends our offering to the highest levels of signal
processing performance.
Our licensees can leverage the capabilities of this
architecture to realize optimal system-on-chip solutions for the next
generation of communications products.'' At the Microprocessor Forum's DSP seminar Thursday, LSI Logic will provide
an initial look at the first core implementation based on the G2 architecture
-- the ZSP600 -- to be available for licensing with system-on-chip designs in
the first quarter of 2002.
A quad-MAC, 6-issue superscalar DSP core, the
ZSP600 delivers up to 1200 MMACs and 1.8 billion instructions per second
-- equipped to meet the ever-increasing signal processing requirements of
today's high performance communications systems. The ZSP600 provides the
highest DSP performance available in an open architecture licensable core. ``The original ZSP core was the pioneer superscalar DSP solution and LSI
Logic's G2 architecture clearly demonstrates the extensibility of that
platform,'' said Will Strauss, president of the market research firm Forward
Concepts (Tempe, AZ).
``The ZSP600 shows that LSI Logic is committed to a
roadmap of continued performance advancement, assuring their customers of a
migration path for their own future products.'' With the ZSP G2 architecture, LSI Logic continues its focus of
facilitating independence from proprietary DSP technology.
Through licensing,
the ZSP open architecture strategy places high performance DSP technology
directly into the hands of system designers.
The ZSP G2 architecture is
supported by the ZSP Solution Partners program, comprising best-in-class third
party application and software vendors, as well as by LSI Logic's ZOpen(TM)
development framework, which simplifies code development and integration. About LSI Logic's ZSP Family of DSP Cores LSI Logic's ZSP superscalar signal processing technology provides the
highest performance open architecture DSP cores available today.
These
licensable and fully synthesizable cores have proven themselves in ASICs and
standard products alike.
The ZSP architecture -- now in its second generation
- has been optimized with respect to code density, compiler performance and
ease of programming.
It is supported by a growing list of software Solution
Partners.
For more information about the ZSP visit the website at
http://www.zsp.com or send e-mail to dsp-mktg@zsp.com. About LSI Logic Corporation LSI Logic Corporation is a leading designer and manufacturer of
communications, consumer and storage semiconductors for applications that
access, interconnect and store data, voice and video. In addition, the company
supplies storage network solutions for the enterprise. LSI Logic is
headquartered at 1551 McCarthy Boulevard, Milpitas, CA 95035, 866-574-5741,
http://www.lsilogic.com .
Notes to Editor:
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